As integrated circuit dimensions decrease and circuit speed increases, new transistor structures have been developed in order to yield good performance at the smaller dimensions. In particular, Silicon-On-Insulator (SOI) devices are known and are generally undoped or very lightly doped silicon on a low K dielectric. SOI devices are characterized by having the active device region insulated from the bulk substrate, generally by a buried oxide layer. The active device region is thereby said to be floating. SOI devices have been developed which consume less power than do bulk CMOS devices, and which operate at higher speeds than do bulk CMOS devices. FIG. 1 shows a prior art SOI device, including bulk substrate 2, buried oxide layer 4, SOI silicon layer 6, field oxide regions 7, gate dielectric layer 8, conducting gate 10, gate sidewall spacers 11, doped source and drain regions 12, and channel region 14. Source and drain regions may overlap the gate region, or gate sidewall spacer technology may be used to provide separation, or underlap, between the gate and the source-drain regions.
For SOI devices having channel lengths below about 50 nm, in particular Fully Depleted Silicon On Insulator (FDSOI) devices, it is very difficult to achieve good short-channel control, i.e., to effectively shut off the transistors in the off state, without significantly thinning down the thickness of the buried layer and the thickness of the SOI silicon layer, which is difficult to reliably achieve with available processes. For a device with SOI silicon thickness of less than 20 nm, an underlap of the source/drain regions with the gate is needed in order to be able to turn off the device. Accordingly, the details of the gate sidewall spacer technology used in the fabrication of such devices are critical to their performance. By way of example, it is known that if doped polysilicon spacers are used in place of nitride spacers (termed a “straddled gate device”), the device DC characteristics improve significantly. The polysilicon spacer which is also doped during source/drain implant serves as a side gate with a lower work function. It behaves like a longer gate when there is no bias applied on the gate (i.e., in the Ioff condition). The polysilicon side gate causes the surface beneath it to invert at much lower applied voltage than the voltage necessary to invert the main channel region, due to the lower work function of the polysilicon. This causes the device to behave like a very short channel device during Ion conditions. The result is a much improved Ion and Ioff. However, when single layer polysilicon gate sidewall spacers are used, the source/drain extension regions reach under the poly spacers and cause an increased overlap capacitance which slows down the AC device performance.
The formation of multiple sidewall spacers, including an inner polysilicon spacer and an outer oxide or nitride spacer, over a metal gate with CD's less than 50 nm, has not to the best knowledge of the inventors been achieved in the prior FDSOI art, but would achieve the desired DC and AC characteristics.